Test Pattern Generators for Distributed and Embedded Built-in Self-Test at Register Transfer Level
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چکیده
Register Transfer Level Vladimir Vorisek Institute of Informatics, Slovak Academy of Sciences [email protected] Abstract The poster presents Ph.D. thesis in the area of Test Pattern Generators (TPGs) for application in distributed and embedded Built-In Self-Test (BIST). The goal of this work is to develop a general scheme of designing built-in TPGs for basic arithmetic elements such as adders, subtracters, multiplexers, comparators at Register Transfer Level (RTL) of circuit description.
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تاریخ انتشار 2001